1. Technical Field
The present invention relates generally to a semiconductor apparatus, and more particularly to a duty cycle correction circuit and a delay locked loop (DLL) circuit including the same.
2. Related Art
A duty cycle of a clock signal indicates a ratio of a time corresponding to a high level period to a time corresponding to a low level period during one cycle of the clock signal. In an integrated circuit operated in synchronization with a clock signal such as a semiconductor integrated circuit, it is very important to maintain a duty cycle of a clock signal at 50:50. That is because, when a duty cycle of a clock signal is not accurately controlled in a synchronous semiconductor apparatus which inputs/outputs data in synchronization with the clock signal, data may be distorted.
FIG. 1 illustrates a known duty cycle correction circuit.
The duty cycle correction circuit includes a duty cycle correction unit 1, a duty cycle detection unit 2, and a control unit 3. The duty cycle detection unit 2 is configured to detect a duty cycle of an output clock signal CLKOUT and output an up-down signal UP_DN, and the control unit 3 is configured to output a duty cycle correction code DCC_CODE in response to the up-down signal UP_DN, according to a counting pulse signal CNT_pulse which is a pulse signal. The duty cycle correction unit 1 is configured to correct the duty cycle of the input clock signal CLKIN according to the duty cycle correction code DCC_CODE, and output the corrected signal as the output clock signal CLKOUT. The method of controlling up/down of signal may include a method in which the level of one signal is classified into a high level and a low level so as to control up/down or a method in which two signals are used to control up/down. Therefore, the up-is down signal UP_DN may be generated according to such methods. In various known duty cycle correction circuits, the method in which the level of one signal is classified into a high level and a low level so as to control up/down is used. However, it is difficult to continuously maintain a state in which the duty cycle is controlled at 50:50. Therefore, the up-down signal UP_DN varies with time between a high level and a low level.
When a high-level period of the output clock signal CLKOUT is larger than a low-level period thereof, the duty cycle correction unit 1 should reduce the high-level period and increase the low-level period. Therefore, the duty cycle detection unit 2 generates the low-level up-down signal UP_DN, and the control unit 3 decreases the value of the duty cycle correction code DCC_CODE in response to the low-level up-down signal UP_DN and the counting pulse signal CNT_pulse. The duty cycle correction unit 1 receives the decreased duty correction code DCC_CODE, and corrects the duty cycle by reducing the high-level period of the input clock signal CLKIN and increasing the low-level period of the input clock signal CLKIN.
The duty cycle correction circuit may be set to be always enabled by activating the counting pulse signal CNT_pulse at all times. In some cases, the duty cycle correction circuit may be set to be selectively enabled by selectively activating the counting pulse signal CNT_pulse.
When the duty cycle is corrected, it is necessary to discriminate whether a variation of the duty cycle per unit time is small or large. The case in which the variation is large is defined as high-frequency noise, and the case in which the variation is small is defined as low-frequency noise. When the duty cycle correction circuit is always enabled, the duty cycle correction circuit may exhibit excellent distortion correction ability for the low-frequency noise, but may cause bang bang jitter for the high-frequency noise.
Therefore, there is a demand for a duty circuit correction circuit capable of detecting a variation of a duty cycle to control the enable of the duty circuit correction circuit.